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EFST
F49B002UA 2 Mbit (256K x 8) 5V Only CMOS Flash Memory
1. FEATURES
Single supply voltage 5V 10% Fast access time: 70/90 ns Compatible with JEDEC standard - Pin-out, packages and software commands compatible with single-power supply Flash Low power consumption - 25mA maximum active current - 25uA typical standby current 100,000 program/erase cycles typically Command register architecture - Byte programming (10us typical) - Sector Erase( sector structure: 16KB, 8KB, 8KB, 96KB, 128KB ) Auto Erase (chip & sector) and Auto Program - Sector erase and Chip erase. - Automatically program and verify data at specified address End of program or erase detection - Data polling - Toggle bits Boot Sector Architecture - U = Upper Boot Sector Packages available: - 32-pin PDIP - 32-pin PLCC
2. ORDERING INFORMATION
Part No F49B002UA-70D F49B002UA-70N Boot Upper Upper Speed 70 ns 70 ns Package PDIP PLCC Part No F49B002UA-90D F49B002UA-90N Boot Upper Upper Speed 90 ns 90 ns Package PDIP PLCC
3. GENERAL DESCRIPTION
The F49B002UA is a 2 Megabit, 5V only CMOS Flash memory device organized as 256K bytes of 8 bits. This device is packaged in standard 32-pin PDIP and 32-pin PLCC. It is designed to be programmed and erased both in system and can in standard EPROM programmers. With access times of 70 ns and 90 ns, the F49B002UA allows the operation of high-speed microprocessors. The device has separate chip enable CE , write enable WE , and output enable OE controls. EFST's memory devices reliably store memory data even after 10,000 program and erase cycles. The F49B002UA is entirely pin and command set compatible with the JEDEC standard for 2 Megabit Flash memory devices. Commands are written to the command register using standard microprocessor write timings. The F49B002UA features a sector erase architecture. The device memory array is divided into 16 Kbytes, 8K bytes, 8Kbytes, 96Kbytes, 128Kbytes. Erase capabilities provide the flexibility to revise the data in the device. A low VCC detector inhibits write operations on loss of power. End of program or erase is detected by the Data Polling of DQ7, or by the Toggle Bit feature on DQ6. Once the program or erase cycle has been successfully completed, the device internally resets to the Read mode.
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4. PIN CONFIGURATIONS 4.1 32-pin PDIP
F49B002UA
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 2 - P in DIP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD WE A17 A14 A13 A8 A9 A11 OE A10 CE DQ 7 DQ 6 DQ 5 DQ 4 DQ 3
4.2
32-pin PLCC
VCC A17 A15 3 A16 A12 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ 0 WE NC
2
1 32 31 30
5 6 7 8 9 10 11 12 13
14 15 16 1 7 18 19 2 0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6
29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE A10 CE DQ7
4.3 Pin Description
Symbol A0~A17 DQ0~DQ7 CE OE
WE
Pin Name Address Input Data Input/Output Chip Enable Output Enable Write Enable No connection Power Supply Ground
Functions To provide memory addresses. To output data when Read and receive data when Write. The outputs are in tri-state when OE or CE is high. To activate the device when CE is low. To gate the data output buffers. To control the Write operations. Unconnected pin To provide power
NC
VCC GND
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5. SECTOR STRUCTURE
Table 1: F49B002UA Sector Address Table Sector SA4 SA3 SA2 SA1 SA0 Sector Size (Kbytes) 16 8 8 96 128 Address range 3C000H-3FFFFH 3A000H-3BFFFH 38000H-39FFFH 20000H-37FFFH 00000H-1FFFFH Sector Address A17 1 1 1 1 0 A16 1 1 1 X X A15 1 1 1 X X A14 1 0 0 X X
F49B002UA
A13 X 1 0 X X
6. FUNCTIONAL BLOCK DIAGRAM
CE OE WE GND VDD A[17:0]
St at e co nt ro l B4 (Boot) 16K B3 (Param.1) 8K B2 (Param.2) 8K Decorder B1 (Main1) 96K B0 (Main2) 128K
I/O buffe r s 3FFFF 3C000 3BFFF 3A000 39FFF 38000 37FFF 20000 1FFFF 00000
DQ[7 :0]
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7. FUNCTIONAL DESCRIPTION 7.1 Device operation
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The register is composed of latches that store the command, address and data information needed
F49B002UA
to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The F49B002UA features various bus operations as Table 2.
Table 2. F49B002UA Operation Modes Selection ADDRESS DESCRIPTION
CE
OE WE
A17 A12 | | A13 A10
A9
A8 | A7 AIN AIN X X
A6
A5 | A2
A1 A0
DQ0~DQ7
Read Write Output Disable Standby Auto-select Notes:
L L L H
L H H X
H L H X See Table 3
Dout DIN High Z High Z
1. L= Logic Low = VIL, H= Logic High = VIH, X= Don't Care, SA= Sector Address, AIN= Address In, DIN = Data In,
Dout = Data Out.
Table 3. F49B002UA Auto-Select Mode (High Voltage Method) ADDRESS DESCRIPTION
CE OE WE
DQ0~DQ7 A3 L H H L L A2 H L H L L A1 L L L L L A0 L L L L H 7FH 7FH 7FH 8CH 00H
A17 | A13 X X X X X
A12 | A10 X X X X X
A9 VID VID VID VID VID
A8 | A4 X X X X X
A6 X X X X X
L (Manufacturer ID:EFST) L L L (Device ID: F49B002UA) L
L L L L L
H H H H H
Notes : 1.Manufacturer and device codes may also be accessed via the software command sequence in Table 4. 2. VID=11.5V to 12.5V.
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Read Mode
To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor's read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Read Command" section for more information. Refer to the AC Read Operations Table 9 for timing specifications and to Figure 5 for the timing diagram. ICC1 in the DC Characteristics Table 8 represents the active current specification for reading array data.
F49B002UA
Resetting the device
The reset command returns the device to Read mode. This is a necessary step after reading the device or manufacturer ID. Note: In these cases, if VID is removed from the A9 pin, the device automatically returns to Read mode and an explicit is not required.
Boot block looking
To keep any system kernel code secure in the boot block, the F49B002UA provides a command to lock the boot block and prevent any accidental erasure or reprogramming. The command sequence is similar to the chip erase sequence except for the last cycle, where 40H must be written into DQ0~DQ7 instead of 10H. The boot block is the only block that can be locked in this way. Whether or not the boot block has been locked can be detected by the command sequence shown in Table 4. This command sequence returns a "1" on DQ0 if the boot block is locked; a "0" if the boot block has not been locked and it is open to erasing and programming.
Write Mode
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to VIL, and OE to VIH. The "Program Command" section has details on programming data to the device using standard command sequences. An erase operation can erase one sector, or the entire device. Table 1 indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Software Command Definitions" section has details on erasing a sector or the entire chip. When the system writes the auto-select command sequence, the device enters the auto-select mode. The system can then read auto-select codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Auto-select Mode and Auto-select Command sections for more information. ICC2 in the DC Characteristics Table 8 represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification Table 10 and timing diagrams for write operations.
Output Disable Mode
With the OE is at a logic high level (VIH), outputs from the devices are disabled. This will cause the output pins in a high impedance state
Standby Mode
When CE held at VCC 0.3V, the device enter CMOS Standby mode. If CE held at VIH, but not within the range of VCC 0.3V, the device will still be in the standby mode, but the standby current will be larger. If the device is deselected during auto algorithm of erasure or programming, the device draws active current ICC2 until the operation is completed. ICC3 in the DC Characteristics Table 8 represents the standby current specification. The device requires standard access time (tCE) for read access from either of these standby modes, before it is ready to read data.
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Auto-select Mode
The auto-select mode provides manufacturer and device identification and sector protection verification, through outputs on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the auto-select codes can also be accessed in-system through the command register. When using programming equipment, this mode requires VID (11.5 V to 12.5 V) on address pin A9. While address pins A3, A2, A1, and A0 must be as shown in Table 3.
F49B002UA
To verify sector protection, all necessary pins have to be set as required in Table 3, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the auto-select codes in-system, the host system can issue the auto-select command via the command register, as shown in Table 4. This method does not require VID. See " Software Command Definitions" for details on using the auto-select mode.
7.2 Software Command Definitions
Writing specific address and data commands or sequences into the command register initiates the device operations. Table 4 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the corresponding timing diagrams in the AC Characteristics section.
Table 4. F49B002UA Software Command Definitions Bus Cycles 1 4 6 6 6 1 3 1st Bus Cycle Addr RA Data RD 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr PA Data PD 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data -
Command Read (4) Program Chip Erase Sector Erase Boot block lock Reset 1(5) Reset 2(5) Auto-select Notes: 1.
5555H AAH 2AAAH 55H 5555H A0H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 40H XXXH F0H -
5555H AAH 2AAAH 55H 5555H F0H See Table 5.
X = don't care RA = Address of memory location to be read. RD = Data to be read at location RA. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector. 2. Except Read command and Auto-select command, all command bus cycles are write operations. 3. Address bits A17-A16 are don't cares. 4. No command cycles required when reading array data. 5. The two Reset command sequences have exactly the same effect, two are provided to meet the requirements of difference companies and a range of applications.
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Table 5. F49B002UA Auto-Select Command Bus Cycles 4 Manufacture ID 4 4 4 Device ID, Upper boot Notes :
1. The fourth cycle of the auto-select command sequence is a read cycle.
F49B002UA
Command
1st Bus Cycle Addr Data
2nd Bus Cycle Addr
3rd Bus Cycle Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data -
6th Bus Cycle Addr Data -
Data Addr
5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H 90H
XX04H 7FH XX08H 7FH XX0CH 7FH XX00H 8CH XX01H 00H
4
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Read Command
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. See the "Read Mode" in the "Read Operations" section for more information. Refer to AC Read Operation Table 9. & Figure 5 for the timing diagram.
F49B002UA
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity. The system can determine the status of the erase operation by using DQ7 or DQ6, See "Programming & Erasing Operation Status" section for more information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. See the Erase/Program Operations Table 10,11 in "AC Characteristics" for parameters.
Program Command
The program command sequence programs one byte into the device. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 and DQ6. See "Write Operation Status" section for more information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. The Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit can't be programmed from a "0" back to a "1". Attempting to do so may halt the operation or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
Sector Erase Command
Sector erase is a six-bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6 (Refer to "Programming & Erasing Operation Status" section for more information on these status bits.) Refer to the Erase/Program Operations Table 10,11 in the "AC Characteristics" section for parameters.
Chip Erase Command
Chip erase is a six-bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm.
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Auto-select Command
The auto-select command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires
F49B002UA
VID on address bit A9. The auto-select command sequence is initiated by writing two unlock cycles, followed by the auto-select command. The device then enters the auto-select mode, and the system may read at any address any number of times, without initiating another command sequence. The read cycles at address 04H, 08H, 0CH, and 00H retrieves the EFST manufacturer ID. A read cycle at address 01H retrieves the device ID. .
7.3 Programming & Erasing Operation Status
The device provides several bits to determine the status of a programming & Erasing operation: DQ7, DQ6, Table 6 and the following subsections describe the functions of these bits. DQ7, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress.
Table 6. Write Operation Status Operation Standard Mode Embedded Program Algorithm Sector erase Embedded Erase Algorithm Chip erase DQ7 (Note1)
DQ7
DQ6 Toggle Toggle Toggle
0 0
Notes: 1. DQ7 require a valid address when reading status information. Refer to the appropriate subsection for further details.
DQ7: Data Polling
During a programming operation, DQ7 returns the complement of the programmed value. During an erase operation, a "0" is produced on DQ7, with this switching to a "1" following the operation. On completion of a programming operation, reading the device after the rising edge of the last - the sixth write enable ( WE ) pulse, returns the value just programmed ("0") on DQ7. If OE is asserted low before the operation is completed, the value of DQ7 many change and it may not represent the correct value. The correct value will be return on the next read cycle, after the system has detected that the value has changed from its complement to the actual value. Figure 14: Data polling flow chart opposite illustrates the actual process. Relevant signal pulse timings are given in Figure 16 : Data polling timing diagram.
DQ6:Toggle BIT I
During program and erase operations, the toggle bit on DQ6 switches between "0" and "1" on successive bus read attempts at any address. The toggling can be detected after the last rising edge of the write enable ___ ( WE ) pulse of an erase or program command sequence and is terminated when the operation is completed. In the case of programming, the last write enable pulse is the fourth; for both the sector erase and chip erase commands, it is the sixth. Figure 15 shows an example use of this function. Relevant signal pulse timings are given in Figure 17: Toggle Bit timing diagram.
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7.4 More Device Operations
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
F49B002UA
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one.
Power Supply Decoupling
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Power-Up Sequence
The device powers up in the Read Mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.
Write Pulse "Glitch" Protection
Noise pulses of less than 15 ns (typical) on CE or WE do not initiate a write cycle.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the device does not accept commands on the rising edge of WE . The internal state machine is automatically reset to reading array data on power-up.
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8. ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . .. . . . . . . . . . . 0C to +70C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +6.5 V A9 (Note 2) .... . . .. . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V All other pins (Note 1). . . . . . . . . . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) .. . .. 200 mA Notes:
F49B002UA
1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 1. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 2. 2. Minimum DC input voltage on pins A9 is -0.5 V. During voltage transitions, A9 may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 1. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Maximum Negative Overshoot Waveform
20 n s +0.8V -0.5V -2.0V 20 n s 20 n s
Figure 2. Maximum Positive Overshoot Waveform
20 n s Vc c +2.0V Vc c +0.5V 2.0V 20 n s 20 n s
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9. OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C VCC Supply Voltages VCC for all devices . . . . . . . . . . . . . . . . . . . . .4.5 V to 5.5 V
F49B002UA
Operating ranges define those limits between which the functionality of the device is guaranteed.
Table 7. Capacitance TA = 25C , f = 1.0 MHz Symbol CIN1 CIN2 COUT Description Input Capacitance Control Pin Capacitance Output Capacitance Conditions VIN = 0V VIN = 0V VOUT = 0V Min. Typ. Max. 6 12 12 Unit pF pF pF
10. DC CHARACTERISTICS
Table 8. DC Characteristics TA = 0C to 70C, VCC = 4.5V to 5.5V Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH1 VLKO Description Input Leakage Current Output Leakage Current VCC Active Read Current VCC Active Write Current CMOS Standby Current TTL Standby Current Input Low Voltage(Note 1) Input High Voltage Voltage for Auto-Select and Temporary Sector Unprotect Output Low Voltage Output High Voltage(TTL) Low VCC Lock-out Voltage Conditions VIN = VSS or VCC, VCC = VCC max. VOUT = VSS or VCC, VCC = VCC max
CE = VIL, OE = VIH, f = 5MHz CE = VIL OE = VIH CE = VCC 0.3V CE = VIH
Min. -0.3 2.0 11.5 2.4 3.2
Typ. 15 25 0.2 -
Max. 10 10 25 30 50 5 0.8 VDD + 0.5 12.5 0.45 -
Unit uA uA mA mA uA mA V V V V V V
VCC =5.0V IOL = 2.1mA IOH = 0.4mA -
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11. AC CHARACTERISTICS
TEST CONDITIONS
F49B002UA
Figure 3. Test Setup
DEVICE UNDER TEST
1.8K +3 .3V
CL
1.3K
DIODE S = I N30 6 4 OR E QU IV AL EN T
CL = 1 0 0 pF In c ludi ng jig c apacit an c e CL = 3 0pF f or F 4 9B0 02 UA
Figure 4. Input Waveforms and Measurement Levels
3.0V 0V 1.5V In p u t Test Poin t s Out pu t
1.5V
A C TE S TIN G : In p u t s a r e d ri v e n a t 3 . 0 V f o r a l o g i c " 1 " a n d 0 V f o r a l o g i c " 0 " In p u t p u l s e r i s e a n d f a l l t i m e s a r e < 5 n s .
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11.1 Read Operation TA = 0C to 70C, VCC = 4.5V~5.5V
Table 9. Read Operations Symbol tRC tACC tCE tOE tDF tOEH Description Read Cycle Time (Note 1) Address to Output Delay
CE to Output Delay CE = OE = VIL
F49B002UA
Conditions
-70 Min. 70 Max. 70 70 30 25 0 10 0 10 0 Min. 90
-90 Max. 90 90 35 30
Unit ns ns ns ns ns ns ns ns
OE = VIL
CE = VIL CE = VIL
OE to Output Delay OE High to Output Float
(Note1) Output Enable Hold Time Read Toggle and Data Polling
tOH
Address to Output hold
CE = OE = VIL
0
Notes :
1. 2. Not 100% tested. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
Figure 5. Read Timing Waveform
tRC Ad dr es s Addresses Stabl e tAC C CE
tOE OE tO EH WE tCE tOH Ou t pu t s High-Z
tDF
High-Z Output Vali d
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11.2 Program/Erase Operation
F49B002UA
Table 10. WE Controlled Program/Erase Operations( TA = 0C to 70C, VCC = 4.5V~5.5V ) Symbol tWC tAS tAH tDS tDH tOES tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write ( OE High to WE low)
CE Setup Time CE Hold Time
-70 Min. 70 0 45 30 0 0 0 0 0 35 20 Max.
-90 Min. 90 0 45 30 0 0 0 0 0 35 20 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns
Write Pulse Width Write Pulse Width High
Notes : 1. Not 100% tested. 2. See the "Programming & Erasing Operation Performance" section for more information.
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F49B002UA
Table 11. CE Controlled Program/Erase Operations(TA = 0C to 70C, VCC = 4.5V~5.5V) Symbol tWC tAS tAH tDS tDH tOES tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Notes : 1. Not 100% tested. 2. See the "Programming & Erasing operation performance" section for more information. Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write
WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High
-70 Min. 70 0 45 35 0 0 0 0 0 35 30 10(typ.) 1.5(typ.) Max.
-90 Min. 90 0 45 35 0 0 0 0 0 35 30 10(typ.) 1.5(typ.) Max. Unit ns ns ns ns ns ns ns ns ns ns ns us sec
Programming Operation(note2) Sector Erase Operation (note2)
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Figure 6. CE Controlled Program Timing Waveform
F49B002UA
5555 for prog ram PA f or p rog ram 2AAA for erase SA for sector erase 5555 f or chip erase
Data Pol li n g PD
Addr es s tWC tWH WE tG HEL tAS tAH
OE tCP tWHWH1 CE tWS tDS tDH Dat a
A0 f o r p r og r a m PD f o r p r o g r a m 30 f or sect or erase 55 for erase 10 f or ch ip erase or 2
tCPH
tBUSY
DQ7 DOUT
Notes : 1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device 2. Figure indicates the last two bus cycles of the command sequence..
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Publication Date : Sep. 2006 Revision: 1.4 17/33
EFST
Figure 7. Write Command Timing Waveform
VCC 5V
F49B002UA
Addr es s
VIH VIL tAS VIH
ADD Valid tAH
WE
VIL tOES tWP tCW C tWPH
CE
VIH VIL tCS tCH VIH VIL tDS tDH DIN
OE
Dat a
VIH VIL
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 18/33
EFST
Figure 8. Embedded Programming Timing Waveform
F49B002UA
5555 for pr og ram PA f or p rog r am SA for sector erase 2AAA for erase 5555 f or chip erase
Data Pol li n g PD
Addr es s tWC tCH CE tGHWL tAS tAH
OE tWP tWHWH1 WE tCS tDS tDH Dat a DQ7 DOUT
A0 f o r p r og r a m PD f o r p r o g r a m 55 for erase 30 f or sect or erase 10 f or c h ip eras e or 2
tWPH
tB US Y
Notes : 1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device 2. Figure indicates the last two bus cycles of the command sequence..
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 19/33
EFST
Figure 9. Embedded Programming Algorithm Flowchart
F49B002UA
Start
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data A0H Address 5555H
In c r e m e n t address
W rite Data PD Address PA
Data Poll from system
No
Verify W ork OK? Ye s
No
Last address? Ye s
Embedded Program Completed
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 20/33
EFST
12. PROGRAMMING & ERASING OPERATION PERFORMANCE
Table 12. Erase And Programming Performance (Note.1)
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles (1) Notes: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25C, 5V. 3.Maximum values measured at 85C, 4.5V. Limits Typ.(2) 1.5 3 10 2 100,000 Max.(3) 5 35 200 5 -
F49B002UA
Unit sec sec Us Sec Cycles
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 21/33
EFST
Figure 10. Embedded Chip Erase Timing Waveform
F49B002UA
Er as e Co m m a n d S e qu en ce ( last t w o cycl e )
Read St at u s Dat a
tWC Addr es s 2AAA h
tAS 5 5 55 h tAH VA VA
CE tCH tGHWL
OE
tWP WE tCS tDS tDH 55 h 1 0h tWPH
tW HW H2
Dat a
In Progr ess Complete
tVCS VC C
Notes : SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data (see "Write Operation Status")
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 22/33
EFST
Figure 11. Embedded Chip Erase Algorithm Flowchart
F49B002UA
Start
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 80H Address 5555H
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 10H Address 5555H
Data Polling from System
No
Data = FFh? Ye s
Embedded Chip Erease Completed
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 23/33
EFST
Figure 12. Embedded Sector Erase Timing Waveform
F49B002UA
Er as e Co m m a n d S e qu en ce ( last t w o cycl e )
Read Statu s Dat a
tWC Addr es s 2AAAh
tAS SA tAH VA VA
CE tGHWL tCH
OE tW HW H1
tWP WE tCS tDS tDH 5 5h tVCS VCC 30 h tWPH
Dat a
In Progress Complete
Notes : SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data (see "Programming & Erasing Operation Status")
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 24/33
EFST
Figure 13. Embedded Sector Erase Algorithm Flowchart
Start
F49B002UA
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 80H Address 5555H
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 30H Address SA Ye s Data Poll from System
No Data = FFh?
Embedded Sector Erease Completed
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 25/33
EFST
PROGRAMMING & ERASING OPERATION STATUS
F49B002UA
Figure 14. Data Polling Algorithm
Start
Read DQ7~DQ0 Add. = VA(1)
No
DQ7 = Data? Yes Pass
Notes : 1. VA =Valid address for programming.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 26/33
EFST
Figure 15. Toggle Bit Algorithm
F49B002UA
Start
Read DQ7~DQ0
Read DQ7~DQ0
(N ote1 )
Ye s
Toggle B it = D Q6 Toggle?
No Pass
Note : 1. Read toggle bit twice to determine whether or not it is toggle.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 27/33
EFST
F49B002UA
Figure 16. Data Polling Timings (During Embedded Algorithms)
tRC Addr es s tAC C tCE VA VA
CE tCH tOE OE tOEH tDF
WE tOH High-Z DQ7
Complement Complement Tr u e Vai l d Dat a
High-Z DQ0~DQ6
Stat u s Data Stat u s Data Tr u e Vai l d Dat a
tWHWH1
or
tWHWH2
Notes : VA = Valid Address. Figure shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 28/33
EFST
F49B002UA
Figure 17. Toggle Bit Timing Waveforms (During Embedded Algorithms)
tRC Addr es s VA tAC C tCE CE tCH tOE OE tOEH tDF VA VA VA
WE tOH DQ6 High-Z
Vaild Status Vaild Status Vaild Data (stops tog gling) Vaild Data
(fi rst re ad )
(sec ond read )
tWHWH1
or
tWHWH2
Notes : VA = Valid Address; not required for DQ6. Figure shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 29/33
EFST
Figure 18. ID Code Read Timing Waveform
F49B002UA
VC C
5V VID
ADD A9 VIH VIL
VIH VIL
ADD A0
tAC C A1 VIH VIL
t AC C
ADD A2 ~ A8 A1 0~ A1 8
VIH VIL VIH VIL VIH tCE
CE
WE
VIL tOE
OE
VIH VIL tOH tDF tOH Data Out 7FH Data Out 00H
Dat a DQ0~DQ7
VIH VIL
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 30/33
EFST
12. PACKAGE DIMENSION 32-LEAD PDIP
F49B002UA
D 32 17
1
16 E
E1
A
B B1
e
A1
L
A2
eA
Dimension in inch
Dimension in mm
A A1 A2 B B1 C E E1 eA L e
Min ------0.015 0.149
------0.590 0.530 0.600 BSC 0.120
Norm ------------0.154 0.018 TYP 0.050 TYP 0.010 ------------15.240 BSC ------0.100 TYP -------
Max 0.210 ------0.159
Min ------0.381 3.785
------0.625 0.560 0.150
O
------14.986 13.462 3.048
Norm ------------3.912 0.457 TYP 1.270 TYP 0.254 ------------------2.540 TYP -------
C
Max 5.33 ------4.039
------15.875 14.224 3.810
O
15
15
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 31/33
EFST
32-LEAD PLCC
F49B002UA
D D1
4 1 32 30
c
5
29
E2 E1 E3
E
E2
13 21
14
20
A1
-C-
A2
0.020" MIN
A
Seating Plane -C-
b e D3 D2 D2 b2
O
0.004
Symbol A A1 A2 b b2 c e E E1 E2 E3 D D1 D2 D3 0O 14.86 13.90 6.05 12.32 11.36 4.78 Min 3.18 1.53 0.33 0.66 0.20
Dimension in mm Norm ------------2.79 REF ------------------1.27 BSC ------14.99 13.97 ------10.16 BSC 12.45 11.43 ------7.62 BSC
Max 3.55 2.41 0.54 0.82 0.36 10 15.11 14.04 6.93 12.57 11.50 5.66
O
Dimension in inch Norm ------------0.110 REF 0.013 ------0.026 ------0.008 ------Min 0.125 0.060 0.050 0O 0.585 0.547 0.238 0.485 0.447 0.188 BSC ------0.590 0.550 ------0.400 BSC 0.490 0.450 ------0.300 BSC
Max 0.140 0.095 0.021 0.032 0.014 10 0.595 0.553 0.273 0.495 0.453 0.223
O
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 32/33
EFST
Important Notice
All rights reserved.
F49B002UA
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of EFST. The contents contained in this document are believed to be accurate at the time of publication. EFST assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by EFST for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of EFST or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. EFST 's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006 Revision: 1.4 33/33

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